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x86 architecture
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521	VIRUS BULLETIN www.virusbtn.com TECHNICAL FEATURE ANTI-UNPACKER TRICKS – PART TEN Peter Ferrie Add to Reading List Source URL: pferrie.host22.com Language: English - Date: 2011-09-27 17:18:26 MOV CPUID JMP Time Stamp Counter INT X86 assembly language Computer architecture X86 instructions X86 architecture
522	ANTI-UNPACKER TRICKS CURRENT Peter Ferrie, Senior Anti-Virus Researcher, Microsoft Corporation Abstract Unpackers are as old as the packers themselves, but Add to Reading List Source URL: pferrie.host22.com Language: English - Date: 2011-09-27 16:43:27 X86 instructions Assembly languages MOV CPUID Segmentation fault X86 Exit JMP X86 assembly language Computer architecture Computing X86 architecture
523	VIRUS BULLETIN www.virusbtn.com VIRUS ANALYSIS 1 DO THE MACARENA Peter Ferrie Symantec Security Response, USA Add to Reading List Source URL: pferrie.host22.com Language: English - Date: 2011-09-27 16:13:20 Mach Mach-O NeXT Portable Executable COM file PowerPC Magic number X86 Computer virus Computer architecture Computing Instruction set architectures
524	RISC vs. CISC – The Post-RISC Vasco Nuno Caio dos Santos Departamento de Informática, Universidade do Minho 4710 – 057 Braga, Portugal [removed] Add to Reading List Source URL: gec.di.uminho.pt Language: English - Date: 2002-01-26 10:53:05 Instruction set architectures Classes of computers Central processing unit Parallel computing Reduced instruction set computing Complex instruction set computing X86 Superscalar Instruction set Computer architecture Computing Computer engineering
525	Microsoft Word - HDA017 DCN CORB size.doc Add to Reading List Source URL: www.crashrecovery.org Language: English - Date: 2012-03-17 07:57:03 Computing Computer architecture Computer hardware X86 architecture Intel
526	Attacks on More Virtual Machines Add to Reading List Source URL: pferrie.host22.com Language: English - Date: 2011-09-27 16:13:20 Central processing unit Virtual machines QEMU VMware Bochs CPUID Emulator Xen Hypervisor System software Software X86 architecture
527	VIRUS BULLETIN www.virusbtn.com TECHNICAL FEATURE ANTI-UNPACKER TRICKS – PART TWO Peter Ferrie Add to Reading List Source URL: pferrie.host22.com Language: English - Date: 2011-09-27 16:43:27 X86 architecture Assembly languages X86 MOV Exit Microsoft-specific exception handling mechanisms JMP CPUID X86 assembly language Computer architecture Computing X86 instructions
528	Advanced Micro Devices ___________________________________________________________ AMD Opteron™ Processor Product Data Sheet • Compatible with Existing 32-Bit Code Base Add to Reading List Source URL: www.orpheuscomputing.com Language: English - Date: 2009-07-22 06:05:13 Computer buses Opteron CPU cache X86 DDR SDRAM SSE2 Synchronous dynamic random-access memory HyperTransport Comparison of AMD processors Computer architecture Computer hardware Computing
529	System Management Bus As the first Intel microprocessor to incorporate a system management bus interface, the Pentium® II Xeon™ processor adds several manageability functions to the Intel product line. Inside the cart Add to Reading List Source URL: www.orpheuscomputing.com Language: English - Date: 2009-07-22 06:44:19 Computer memory Microprocessors X86 architecture Intel Core Xeon Pentium II Platform Environment Control Interface Read-only memory Multi-core processor Computer hardware Computing Electronic engineering
530	RHEL Kernel Performance Optimization, Characterization and Tuning Larry Woodman John Shakshober Agenda Add to Reading List Source URL: www.redhat.com Language: English - Date: 2008-06-26 16:15:25 Memory management X86 architecture X86-64 X86 Page Central processing unit Non-Uniform Memory Access Computer architecture Computing Computer hardware

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